Performance Analysis and Verification of Multipliers

Multiplication is a fundamental operation in most arithmetic computing systems. Multipliers have large area, long latency and consume considerable power. The number of gates per chip area is constantly increasing, while the gate switching energy does not decrease at the same rate, so the power dissipation rises and heat removal becomes more difficult and expensive. Then, to limit the power dissipation, alternative solutions at each level of abstraction are used. At the algorithm and architecture level, this paper addresses Low-Power, High Speed and Less Area multiplier design systematically from two aspects: internal efforts considering multiplier architectures and external efforts considering input data characteristics.  For internal efforts, we consider recoding optimization for partial product generation, operand representation optimization, and structure optimization of partial product reduction. For external efforts, we consider signal gating to deactivate portions of a full-precision multiplier.  Several multiplier types are studied:  array multipliers, wallace multipliers, booth multiplier. In accordance to that we specify that the comparison and verification of the multiplier on basics of time delay, power and area.

Optimization of Speed using Compressors

The main objective of this Review is to provide high speed solutions for Very Large Scale Integration (VLSI) designers. Especially, we want focuses on the reduction of the time delay, which is showing an ever-increasing growth with the scaling down of the technologies. Various techniques at the different levels of the design process have been implemented to reduce the time delay at the circuit, architectural and system level. The high performance is obtained by using a new hierarchical structure, These adders are called compressors. These compressors make the multipliers faster as compared to the conventional design .